1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device in which a plurality of chips are stacked and packaged and a method of generating a chip enable signal thereof.
2. Description of Related Art
In general, a semiconductor memory device is fabricated by packaging a single chip. Thus, both a memory portion for storing data and a control portion for controlling the input/output of data in/from the memory portion are integrated in the single chip.
However, a semiconductor memory device packaged by stacking a plurality of chips has recently been introduced. In the semiconductor memory device, a control portion is provided in one of the chips, and a memory portion is provided in each of the remaining chips.
In the semiconductor memory device in which the chips are stacked and packaged, each of the chips should include a chip enable signal generation circuit to enable the input/output of data in/from one of the chips. Chip enable signal generation circuits included in the chips should have the same configuration so that the respective chips can be fabricated using the same process. When the respective chip enable signal generation circuits have different configurations, additional masks should be prepared to form different mask patterns required for the respective chips.
FIG. 1 is a diagram showing the configuration of a conventional semiconductor memory device in which a plurality of chips are stacked.
Referring to FIG. 1, the semiconductor memory device includes an i+1 number of memory chips 10-1 to 10-i and an interface chip 12. Each of the memory chips 10-1 to 10-i includes a memory cell array portion (not shown) and the corresponding one of counters CNT1 to CNTi, and the interface chip 12 includes a controller (not shown) and a chip identification (ID) code generator CIG. Also, the counters CNT1 to CNTi of the memory chips 10-1 to 10-i are cascade-connected to one another.
Functions of the semiconductor memory device shown in FIG. 1 will now be described.
The chip ID code generator CIG generates a start counting value as a chip ID code. The counter CNT1 of the memory chip 10-1 receives the start counting value, performs a counting operation, and outputs a 1-added output value. The counter CNT2 receives the output value of the counter CNT1, performs a counting operation, and outputs a 1-added output value. In the same manner, the counters 10-1 to 10-i sequentially output 1-added values. Thus, the counters 10-1 to 10-i output respectively different output values and generate chip enable signals for enabling operation of the corresponding memory chip using the output value and an externally applied chip ID signal (e.g., an address signal).
The conventional semiconductor memory device shown in FIG. 1 has been published in detail in U.S. Patent Publication No. 2004/0257847.
In the foregoing conventional semiconductor memory device, the respective memory chips 10-1 to 10-i have the same configuration, so that the memory chips 10-1 to 10-i can be fabricated using the same fabrication process. However, since the counters CNT1 to CNTi of the memory chips 10-1 to 10-i are cascade-connected to one another, a next counter generates a delayed output value due to previous counters, thus adversely affecting high-speed operation of the semiconductor memory device. Also, the circuit configuration of the semiconductor memory device becomes complicated because each of the counters CNT1 to CNTi includes flip-flops.